1. Field of the Invention
The present invention concerns a method for synchronization between two networks.
2. Description of the Related Art
Communication networks are known, formed by several serial communication buses which are for example in accordance with IEEE 1394-1995.
IEEE 1394-1995 defines a high-throughput serial communication bus which must allow a low-cost interconnection between cards in the same item of equipment, cards in different equipments and external peripheries.
There are two physical environments for a serial bus: the cable and the back plane (or interconnection card). Interconnection by cable makes possible to connect up to sixteen different items of equipment at a maximum distance of 4.5 meters. This allows a total distance of 72 meters between the furthest-away items of equipment. The speed of transmission over the cable can be 100, 200 or even 400 Mbps. The transmission speeds on a back plane can be 25 (24,576) and 50 Mbps. The access mechanism to the bus has been specified in this standard to allow equitable use of the bus by all the items of equipment connected thereto. In addition to the conventional functions of reading/writing, the serial bus offers advanced synchronized services such as the transportation of isochronous data (guaranteeing a transmission time and a bandwidth), and are overall time base with a precision less than one microsecond for synchronizing data and events.
The serial communication buses are organized in a network, that is to say they are connected together by interconnection elements which are referred to as “bridges”.
The bridges connecting serial communication buses are in particular the subject of the standard P1394.1, which is under discussion.
A bridge has two items of interconnection equipment or nodes, also referred to as “portals”, which are each connected to one of the two serial communication buses.
These two items of interconnection equipment communicate with each other through links of different natures: wired, optical, radio etc.
The bus network thus forms a structure arranged hierarchically in a tree in which one of the buses is considered to be the upper bus, referred to as the “root” bus, from which the various other buses extend, constituting the branches of the hierarchical tree structure.
Each serial communication bus in such network connects together different peripherals such as printers, computers, servers, scanners, video tape recorders, decoders (or set top boxes), television receivers, digital cameras, camcorders, digital photographic apparatus, telephones, audio/video players, etc.
These peripherals are generally referred to as nodes.
On each serial communication bus in the network, each peripheral or node has an internal clock (oscillator) from which clock pulses are generated at a clock frequency, for example 24.576 MHz.
On each serial communication bus in a network, one of the nodes is referred to as the “Cycle Master”, and the cycle master node on the “root” bus is referred to as the “Network cycle master”.
All “cycle master” nodes in the network generate cycles using their internal clocks and thus the duration of these cycles will depend on the precision of each particular clock. The duration of the cycle denoted T, peculiar to a bus, is equal to an integer number ninit of clock pulses common or not to all the buses and which is multiplied by the inverse of the frequency of the internal clock of the “cycle master” node of the bus.
The duration of the isochronous cycle T is thus for example 125 microseconds±12,5 ns.
The synchronization of the isochronous cycles on a serial communication bus is checked by the “cycle master” node of the bus under consideration, which can be defined as a synchronization node of the bus.
The “cycle master” node will then generate, on the bus, every 125 microseconds±12,5 ns, a signal referred to as the “cycle start packet”, which corresponds to a synchronization message. The frequency of generation of this signal is supplied by an internal clock, derived from its local clock at 24.576 MHz, with a frequency equal to 8 kHz±100 ppm that the “cycle master” node keeps up to date.
This signal on the bus, makes it possible to synchronize other nodes with respect to the “cycle master” node and also inform them that they can transmit isochronous data to other nodes on the same bus or one or more of the other buses, which are connected to the bus under consideration respectively by one or more bridges.
It should be noted that, when an isochronous cycle starts, whilst the data are being transmitted over the bus, the generation of the cycle start packet is delayed, that's generates a significant shift of the cycle start.
Considering that such a shift is very often unacceptable, the delay time on transmission of a cycle start signal is taken into account in a register referred to as the cycle time register. Thus, the Cycle Master makes through the cycle starts signal, a copy of its cycle time register for all isochronous nodes connected to the bus.
Each node which is capable of transmitting isochronous data has such cycle time register.
The cycle time register, also abbreviated to CTR, has a size of 32 bits, the first twelve bits represent a counter modulo 3072 which is incremented at each period of the local clock which frequency is 24.576 MHz.
The following thirteen bits of the cycle time register CTR represents a counter of the number of isochronous cycles transmitted at a frequency of 8 kHz.
The last seven bits of the cycle time register CTR count the number of seconds.
When the cycle start signal reaches all the nodes on the bus able to transmit isochronous data, they copy, into a register, the content of the cycle time register CTR of the “cycle master” node of the bus contained in the cycle start signal.
The maximum difference is in fact obtained when the internal clock frequency of one of the peripherals is 24.576 MHz+100 ppm and the other frequency of the other peripheral is 24.576 MHz−100 ppm.
For example, the frequency of the internal clock of the “network cycle master”, denoted CMA, of the “root” bus has a value of 24.576 MHz+100 ppm, whilst that of the internal clock the “cycle master” CMB, of a lower-level bus which is directly connected to the “root” bus by a bridge has a value of 24.576 MHz-100 ppm.
The communication networks formed by serial communication buses allow the transmission of synchronized data using cycles of the buses under consideration. The buses are for example used for transmitting real-time data of the audio/video type.
Thus, when the two “cycle masters” previously mentioned, denoted CMA and CMB, are taken with their respective clock frequency values, namely 24.576 MHz+100 ppm and 24.576 MHz−100 ppm, the duration of the cycles calculated for each of the “cycle masters”, denoted respectively TA and TB, are different, because of the different frequencies of the internal clocks of these “cycle masters”.
FIG. 1 also illustrates this phenomenon and shows, on two superimposed axes, for the same integer number ninit such that TA A=ninit/FA and TB=ninit/FB, where F designates the clock frequency of the “cycle master” under consideration, a cycle of duration TB greater than the cycle TA.
This figure depicts, above the first two cycles of the bus, the numbers of two data packets identified by the numbers 1 and 2.
It should also be noted that the case depicted in FIG. 1 is very unlikely in reality since it envisages a nil phase difference at the origin of each of the first cycles of the two buses.
However, a comparison of these two axes shows a relative shift in the start of each cycle which corresponds in fact to a change in the phase shift (nil at the origin of the times in the figure) in the course of time between the cycles under consideration.
In addition, two arrows have been depicted between the two axes in order to indicate the delay with which the data packets denoted 1 and 2 are transmitted over the bus B after having crossed the bridge connecting buses A and B together. It is in fact estimated that the delay depicted here is equivalent to two cycles and is explained by the time necessary for the processing of the packets in the bridge before they are transmitted over the bus B.
Thus, having regard to the relative time offset noted between the respective cycles of buses A and B, at the end of a certain number of cycles, a data packet emanating from bus A will not be transmitted to bus B.
The non-transmission of this data packet may therefore be highly prejudicial for real-time data of the audio and/or video type.
This is because, with data for example of the video type, it is very important to correctly transmit all the video data packets so as not to degrade the video image obtained from the transmitted packets.
In general terms, if the duration TA is less than TB, then a data packet will be lost at the end of a certain number of cycles, which means that one cycle will have been lost, and if, on the other hand, TA is greater than TB, then no data packet will be transmitted during one of the cycles and there will therefore be an empty cycle, giving rise, thereby, to a loss of synchronization in the processing of real-time data of the audio and/or video type.
The problem of offset mentioned above is currently being studied within the Bridge working group of the IEEE 1394 (standard P1394.1) standardization committee.
Solutions have been proposed, notably by the Philips company in January and March 1998 within this working group, in the form of two contributions referenced Br008r00.pdf and Br015r00.pdf entitled: “Synchronizing Cycle Master to External Timing Information via Cycle Slave”.
In the context of this solution, a bridge consisting of two connecting nodes or “portals” connect two serial communication buses, one being referred to as the master bus and the other the slave bus respectively referenced bA and bB. In a known fashion, the isochronous cycles of each serial communication bus bA and bB are synchronized by virtue of the mechanism for transmitting the cycle start signals generated by the “cycle master” synchronization nodes of each of the buses. In order to solve the problem mentioned above and to synchronize buses bA and bB together, Philips proposes to transmit, at the connecting node connected to the bus bA, a signal referred to as “cycle reset” intended for the interconnecting node connected to the bus bB.
This signal indicates the start of a new isochronous cycle which corresponds to the change to zero of the first twelve bits of the cycle time register CTR at the interconnecting node connected to the bus bA. These first twelve bits are referred to as “cycle offset”.
The interconnecting node connected to the bus bB receiving the “cycle reset” signal recovers the value of the counter “cycle offset” from its cycle time register CTR and stores it in a register called “timer offset”.
The register “timer offset” therefore contains the value of the offset between the isochronous cycles of the master bus bA and slave bus bB.
Next, the interconnecting node connected to the bus bB, copies the content of the register “timer offset” into a register called “timer adjustment” of the “cycle master” node of the slave bus bB.
The “cycle master” node of the slave bus b. then reads the content of its cycle time register CTR, subtracts therefrom the value of the content of the register “timer adjustment” and records this result in its cycle time register CTR.
This method makes it possible to keep the registers “cycle offset” of the “cycle master” nodes of buses bA and be synchronized at each transmission of the isochronous cycle, which prevents offsets due to lack of precision in their respective clocks.
However, this solution has a drawback since the transmission of the signal “cycle reset” from the interconnecting node connected to the bus bA to the interconnecting node connected to the bus bA must be instantaneous or of relatively short duration known with precision in order not to introduce any error into the evaluation of the start of the isochronous cycle.
This solution is applicable when the two interconnecting nodes of the bridge form part of the same physical entity or are not distant from each other.
However, when these two items of interconnecting equipment communicate with each other for example by radio, by optical link or through a network the transmission of the signal “cycle reset” is not instantaneous and suffers various transmission delays.
In addition, in the case of transmission by radio, it is not possible to guarantee good reception of the signal because of interference on the radio channel.
Consequently, it would be advantageous to find a method for synchronizing two serial communication buses connected together by a bridge, whatever the communication medium used for the transmission of information between the two interconnection nodes constituting the bridge.
In general terms, this invention solves the problem of synchronization between the two synchronization nodes or “cycle masters” of the serial communication buses under consideration.